I. Field of the Disclosure
The technology of the present application relates generally to a memory access controller and related systems and methods for optimizing memory access times in a processor-based system.
II. Background
It is common for processor-based systems, including central processing unit (CPU) based systems, to use dynamic memory for system memory. Dynamic memory is less expensive than static memory, because only one transistor is typically required per memory bit in dynamic memory as opposed to multiple transistors typically required per bit of static memory. However, use of dynamic memory has a tradeoff. Dynamic memory access times are typically longer than static memory access times. Accessing dynamic memory involves two discrete tasks, both of which require processing time. First, the memory page (i.e. row) corresponding to the desired memory location in a memory bank to be accessed is opened. This is also known as a “row select,” referring to a two-dimensional row and column memory arrangement. Second, the desired memory location within the memory page is accessed. This is also known as a “column select.” Increased memory access times incurred by use of dynamic memory can impact CPU performance both in terms of reduced bandwidth and number of instructions executed in a given time (e.g. million instructions per second (MIPS)).
To mitigate increased memory access times when employing dynamic memory in processor-based systems, memory controllers can be configured to keep or leave a memory page within a given memory bank open after an access to the memory page. Keeping or leaving a memory page open after an access in a memory bank can improve memory access time performance if contiguous memory accesses are to the same memory page. Processing time is not required to close the memory page and reopen it for subsequent accesses. However, a tradeoff exists by keeping or leaving a memory page open in a memory bank after an access. If, for example, a CPU wants to access data from a different memory page in the same memory bank, three tasks, as opposed to two tasks, must be performed. First, the currently open memory page must be closed in the memory bank. Next, the new memory page containing the desired memory location to be accessed must be opened. Then, the desired memory location within the memory page is accessed. The additional processing time incurred in closing a previously accessed memory page before a new memory page can be opened results in reduced bandwidth and reduces MIPS for the CPU.
Configuring a memory controller to keep or leave a memory page open after an access may be ideal for certain memory applications, particularly those that involve accessing contiguous memory locations, such as video, graphics, and display memory applications, and other applications, as examples. In these scenarios, memory page closes occur less often, because contiguous memory accesses are to the same memory page in a given memory bank. However, configuring a memory controller to keep or leave a memory page open after a memory access may not be ideal for other memory access applications, such as cache enabled CPU accesses for example. This is because it is unlikely that contiguous memory accesses will be to the same memory page in a given memory bank. Thus, memory access time will be increased due to the increased processing time involved in closing a previously accessed memory page before a new memory page can be opened.